1. Field of the Invention
The present invention relates to a processor for executing various arithmetic operations, and more particularly to an arrayed processor comprising an array of processing elements whose individual operations and mutual connections are variable.
2. Description of the Related Art
At present, products called CPU (Central Processing Unit) and MPU (Micro Processor Unit) are used in the art as processor units capable of performing various data processing processes.
In a data processing system using such a processor unit, a plurality of application programs in which a plurality of instruction codes are described and various processing data are stored in a memory device, and the processor unit sequentially reads instruction codes and processing data from the memory device and successively carries out a plurality of processing tasks.
While a solo processor unit can perform various data processing processes, the processor unit needs to successively carry out a plurality of processing tasks. Since the processor unit is required to read instruction codes from the memory device in each of the processing tasks, it is difficult for the processor unit to perform complex data processing operations at a high speed.
If only one data processing task is required to be performed, then a logic circuit may be hardware-implemented to carry out such one data processing task. With such a logic circuit used, a processor unit is not needed to sequentially read a plurality of instruction codes from a memory device and successively carry out a plurality of processing operations. Therefore, it is possible to perform a complex data processing task at a high speed. However, only one data processing task can be carried out at a high speed.
In summary, a data processing system capable of switching between application programs can perform various data processing processes, but finds it difficult to perform data processing operations at a high speed because the data processing system has a fixed hardware arrangement. A hardware-implemented logic circuit is capable of carrying out data processing processes at a high speed, but can perform only one data processing task as its application program cannot be changed.
To solve the above problems, the applicant has devised an arrayed processor as a processor unit whose hardware arrangement changes depending on the software to be executed, and filed Japanese patent application No. 2000-043202 for such an arrayed processor.
Japanese patent application No. 2000-043202 was not laid open at the time the Japanese application corresponding to the present U.S. patent application was filed, it does not constitute known prior art for the present application, but constitute unknown related art for the present application.
The arrayed processor disclosed in Japanese patent application No. 2000-043202 comprises a matrix of small-scale arithmetic logic units whose individual operations and mutual connections are variable depending on a plurality of instruction codes sequentially described in application programs.
Therefore, when an application program changes to another application program, the hardware arrangement of the arrayed processor changes, allowing the arrayed processor to perform various data processing processes. The arrayed processor can carry out data processing tasks at a high speed because a number of small-scale processing elements as hardware elements carry out simple processing operations in parallel.
While the arrayed processor can carry out various data processing tasks at a high speed, some capability of the arrayed processor may be wasted depending on application programs and processing data.
For example, if an arrayed processor comprises a matrix of arithmetic logic units each for carrying out 8-bit processing processes, then it can perform processing tasks most efficiently when processing data are of 8 bits, but some of the processing capability of the arithmetic logic units is wasted when processing data are of 4 or 2 bits.
One solution to the above problem would be to construct an arrayed processor of a number of arithmetic logic units each carrying out 1-bit processing processes. However, if processing data are of a plurality of bits, then since a number of arithmetic logic units need to be used, the processing capability of the arrayed processor would be lowered in most data processing applications.